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Integrated Circuit Systems, Inc.
ICS9112-06/07
Low Skew Output Buffer
General Description
The ICS9112 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 75 MHz (30 to 90mHz for 5V operation). ICS9112 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/350 pS, the part acts as a zero delay buffer. The ICS9112 comes in with two different options; dash 06 and dash 07. The dash 07 is available in a 16 pin 150 mil SOIC package. It has two banks of four outputs controlled by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output buffers (see table below for functionality). The dash 06 is an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, both ICS9112-06 and -07 will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.
Features
* * * * * * * Zero input - output delay Frequency range 25 - 75 MHz (3.3V), 30-90MHz (5.0V) Less than 200 ps Jitter between outputs Skew controlled outputs Skew less than 250 ps between outputs Available in 8 or 16 pin versions, 150 mil SOIC packages 3.3V 10%, 5.0V10% operation
Pin Configuration
16 pin SOIC
Block Diagram
8 pin SOIC
Functionality (-07)
FS2 0 0 1 1 FS1 0 1 0 1 CLKA (1, 4) Tristate Driven Test Mode Driven CLKB (1, 4) Tristate Tristate Test Mode Driven CLKOUT Driven Driven Test Mode Driven Output Source PLL PL L REF PLL PLL Shutdown N N Y N
9112-06 9112-07 Rev H 1/22/99
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9112-06/07
Pin Descriptions
PIN NUMBER 1 2 3 4, 13 5, 12 6 7 8 9 10 11 14 15 16 PIN NAME REF2 CLKA23 CLKA13 VDD GND CLKB1 CLKB2 FS2 FS1
4 4 3 3 3 3 3 3 3
TYPE IN OUT OUT PWR PWR OUT OUT IN IN OUT OUT OUT OUT OUT
DESCRIPTION Input reference frequency. 5V tolerant input Buffered clock output, Bank A Buffered clock output, Bank A 3.3V supply Ground Buffered clock output. Bank B Buffered clock output. Bank B Select input, bit 2 Select input, bit 1 Buffered clock output. Bank B Buffered clock output. Bank B Buffered clock output, Bank A Buffered clock output, Bank A Buffered clock output, internal feedback on this pin
CLKB3 CLKB4
CLKA2 CLKA3
CLKOUT
PIN NUMBER 1 2 3 4 5 6 7 8
PIN NAME REF2 CLK23 CLK33 GND CLK3 VDD CLK4
3 3
TYPE IN OUT OUT PWR OUT PWR OUT OUT
DESCRIPTION Input reference frequency. 5V tolarant input Buffered clock output Buffered clock output Ground Buffered clock output 3.3v Supply Buffered clock output Buffered clock output. Internal feedback on this pin
CLK6 (CLKOUT)3
Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 4. Weak pull-ups on these inputs
PB
ICS9112-06/07
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage1 SYMBOL VIL VIH IIL IIH VOL VOH IDD IDD VIN=0V VIN=VDD IOL = 8mA IOH = 8mA REF = 0 MHz Unloaded oututs at 66.66 MHz SEL inputs at VDD or GND 2.4 2.0 19 0.10 0.25 2.9 37.0 16.0 75.0 40.0 50.0 100.0 0.4 TEST CONDITIONS MIN TYP MAX 0.8 UNITS V V A A V V A mA
Output High Voltage1 Power Down Supply Current Supply Current
Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. All Skew specifications are mesured with a 50 transmission line, load teminated with 50 to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
3
ICS9112-06/07
Switching Characteristics (3.3V Continued)
PARAMETER Output period Output period Duty Cycle1 Rise Time1 Rise Time1 Fall Time1 Fall Time1 Delay, REF Rising Edge to CLKOUT Rising Edge1, 2 Output to Output Skew1 Device to Device Skew1 Cycle to Cycle Jitter1 PLL Lock Time1 Jitter; Absolute Jitter1 Jitter; 1 - Sigma1 SYMBOL t1 t1 Dt1 tr1 tr2 tf1 tf2 Dr1 Tskew Tdsk-Tdsk Tcyc-Tcyc tLOCK Tjabs Tj1s CONDITION With CL=30pF With CL=20pF Measured at 1.4V; CL=30pF Measured between 0.8V and 2.0V: CL=30pF Measured between 0.8V and 2.0V: CL=20pF Measured between 2.0V and 0.8V; CL=30pF Measured between 2.0V and 0.8V; CL=20pF Measured at VDD/2 All outputs equally loaded, CL=20pF Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66 MHz, loaded outputs Stable power supply, valid clock presented on REF pin @ 10,000 cycles CL=30pF F=20 - 50MHz @ 10,000 cycles CL=30pF F=20 - 50MHz -100 70 14 0 MIN 40.00 (25) 40.00 (25) 40.0 49.1 1.70 1.4 1.50 1.3 0 TYP MA X 20.00 (50) 13.33 (75) 60.0 2.50 2.0 2.50 2.0 350 250 700 200 1.0 10 0 30 ms ps ps UNITS ns (MHz) ns (MHz) % ns ns ns ns ps ps ps
Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. REF input has a threshold voltage of VDD/2 3. All parameters expected with loaded outputs
PB
ICS9112-06/07
Electrical Characteristics at 5.0V
VDD = 4.5 - 5.5 V, TA = 0 - 70 C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage1 SYMBOL VIL VIH IIL IIH VOL VOH IDD IDD VIN=0V VIN=VDD IOL = 10mA IOH = 10mA REF = 0 MHz Unloaded oututs at 66.66 MHz SEL inputs at VDD or GND 3.4 2.0 -100 -19 0.10 0.25 4.0 48 24 150 65 100.0 0.4 TEST CONDITIONS MIN TYP MAX 0.8 UNITS V V A A V V A mA
Output High Voltage1 Power Down Supply Current Supply Current
Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. All Skew specifications are mesured with a 50 transmission line, load teminated with 50 to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
5
ICS9112-06/07
Switching Characteristics (5.0V Continued)
PARAMETER Output period Output period Duty Cycle1 Rise Time1 Rise Time1 Fall Time1 Fall Time1 Delay, REF Rising Edge to CLKOUT Rising Edge1, 2 Output to Output Skew1 Device to Device Skew1 Cycle to Cycle Jitter1 PLL Lock Time1 Jitter; Absolute Jitter1 Jitter; 1 - Sigma1 SYMBOL t1 t1 Dt1 tr1 tr2 tf1 tf2 Dr1 Tskew Tdsk-Tdsk Tcyc-Tcyc tLOCK Tjabs Tj1s CONDITION With CL=30pF With CL=20pF Measured at 1.4V; CL=30pF Measured between 0.8V and 2.0V: CL=30pF Measured between 0.8V and 2.0V: CL=20pF Measured between 2.0V and 0.8V; CL=30pF Measured between 2.0V and 0.8V; CL=20pF Measured at VDD/2 All outputs equally loaded, CL=20pF Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66 MHz, loaded outputs Stable power supply, valid clock presented on REF pin @ 10,000 cycles CL=30pF F=20 - 50MHz @ 10,000 cycles CL=30pF F=20 - 50MHz -200 80 14 -400 MIN 60.00 (30) 60.00 (30) 40.0 49.1 1.5 0.7 1.2 0.9 0 80 0 TYP MA X 20.00 (50) 16.11 (90) 60 2.3 1.8 2. 3 1.8 +400 250 700 300 1.5 10 0 30 ms ps ps UNITS ns (MHz) ns (MHz) % ns ns ns ns ps ps ps
Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. REF input has a threshold voltage of VDD/2 3. All parameters expected with loaded outputs
PB
ICS9112-06/07
Application Suggestion:
ICS9112 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess jitter to the outputs of ICS9112. Below is a recommended lay out to alleviate any addition noise. Figure below depicts only ICS911207, but similar techniques could be used for dash 06. For additional information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line stability.
7
ICS9112-06/07
8 pin SOIC Package
16-Pin SOIC Package
Ordering Information
ICS9112M-06 ICS9112M-07
Example:
ICS XXXX M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
PB
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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